Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5
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A developer has announced a port of the Project Oberon system to the RISC-V architecture, replacing the original RISC-5. This development demonstrates the OS’s adaptability to new hardware and could influence future educational and research projects.

A developer has shared a version of the Project Oberon operating system ported to the RISC-V architecture, replacing the original RISC-5 hardware platform. This development confirms that Oberon, historically tied to specific hardware, can now run on a widely adopted open-source CPU architecture, which may expand its use in academic and research settings.

The port was shared via a Show HN post by an independent developer, demonstrating that the Oberon system can operate on RISC-V hardware. The project involves adapting the OS’s kernel and system components to support RISC-V’s instruction set and hardware interfaces. The original Oberon OS was designed for the RISC-5 platform, a less common architecture, primarily used in academic projects. The developer has provided source code and documentation to support the port, emphasizing its experimental nature. It is not yet clear whether this port is fully functional or suitable for production use, but it represents a significant step in demonstrating the OS’s hardware flexibility.
According to the developer, the port was achieved by modifying the system’s low-level hardware interface layer and recompiling the kernel for RISC-V. The project aims to preserve Oberon’s simplicity and educational value while leveraging the benefits of RISC-V’s open architecture. The community response has been positive, with interest in further testing and potential applications in education and research environments.
While the port is still in early stages, it highlights the potential for legacy or niche operating systems to adapt to modern, open hardware platforms, broadening their relevance and application scope.
At a glance
updateWhen: announced March 2024
The developmentA Show HN post revealed a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 architecture.

Implications for Hardware Compatibility and Education

This development is significant because it demonstrates that legacy operating systems like Oberon can be ported to modern, open-source hardware architectures such as RISC-V. This could lead to increased adoption in academic settings and research projects that prioritize open hardware and software. It also showcases the flexibility of Oberon, which was originally designed for specific hardware, and may inspire similar efforts to adapt other specialized or educational OSes to new platforms. The move aligns with broader trends towards open-source hardware and software, potentially reducing dependence on proprietary systems and fostering innovation in system design and education.
Furthermore, this port could serve as a valuable learning tool for students and researchers interested in operating system development, hardware-software integration, and open architecture ecosystems.
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Background on Project Oberon and RISC-V Porting Efforts

Project Oberon was originally developed in the 1980s by Niklaus Wirth and colleagues at ETH Zurich as both an operating system and programming environment, emphasizing simplicity and educational value. Historically, Oberon ran on custom hardware based on the RISC-5 architecture, which was designed for research and educational purposes. Over the years, efforts to modernize Oberon have included porting it to various hardware platforms, but it remained largely tied to specific architectures.
RISC-V, an open-source instruction set architecture (ISA), has gained popularity since its introduction in 2010 due to its flexibility, modularity, and openness. Its adoption by academia, industry, and hobbyists has led to numerous projects porting operating systems and software to RISC-V hardware.
In this context, the recent port of Oberon to RISC-V signifies a convergence of two longstanding initiatives: preserving a classic educational OS while leveraging modern, open hardware platforms. The port was first shared publicly in March 2024 through a Show HN post, with the developer providing source code and documentation for community review and testing.

“Porting Oberon to RISC-V was a challenging but rewarding process that showed the OS’s adaptability to new hardware architectures.”

— Independent Developer

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Extent of Functionality and Stability of the RISC-V Port

It is not yet clear how fully functional or stable the RISC-V port of Oberon is. The developer has indicated that the project is in early testing stages, and comprehensive performance or compatibility assessments are still pending. Details about which system components work reliably and which require further development remain unconfirmed.
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Next Steps for Testing and Community Involvement

The developer plans to continue refining the port, addressing stability and compatibility issues. Community testing and feedback are encouraged to identify bugs and improve functionality. Further documentation and potential integration with different RISC-V hardware platforms are expected. The project could also inspire similar efforts to port other educational or legacy operating systems to open hardware architectures.
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Key Questions

Can I run the RISC-V version of Oberon on my hardware now?

The port is in early stages, and it may require specific RISC-V hardware and technical expertise to set up and run. The developer has shared source code and documentation for testing purposes.

What are the benefits of running Oberon on RISC-V?

Running Oberon on RISC-V demonstrates the OS’s adaptability and can serve as an educational tool for understanding OS design on open hardware platforms.

Will this port support all features of the original Oberon system?

It is currently unclear how complete the port is; some features may still be under development or testing, and full functionality has not been confirmed.

Does this mean Oberon is moving away from proprietary hardware?

This port emphasizes the potential for open hardware support, aligning with Oberon’s educational and research goals, but it does not imply a full transition away from all hardware platforms.

Could this port influence other legacy operating systems?

Potentially, yes. Demonstrating that Oberon can run on RISC-V might inspire similar efforts for other systems seeking hardware modernization or open hardware support.

Source: hn

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